NXP T2080 / CW VPX3-152: VxWorks 7 64-bit boot support#746
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dgarske wants to merge 1 commit intowolfSSL:masterfrom
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NXP T2080 / CW VPX3-152: VxWorks 7 64-bit boot support#746dgarske wants to merge 1 commit intowolfSSL:masterfrom
dgarske wants to merge 1 commit intowolfSSL:masterfrom
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Pull request overview
This PR fixes multiple early-boot issues for NXP QorIQ T2080/e6500 targets to enable wolfBoot to boot successfully on the Curtiss‑Wright VPX3‑152 (256 MB NOR @ 0xF0000000, CCSRBAR relocated to 0xEF000000), while keeping NAII 68PPC2 behavior intact.
Changes:
- Corrects high-address loads on e6500 (avoid
lissign-extension) and adjusts TLB1/CCSRBAR relocation sequencing to prevent faults. - Adds VPX3‑152-specific TLB sizing/mapping changes to avoid TLB multi-hit overlap with 256 MB NOR.
- Updates T2080 HAL for VPX3‑152 constraints (disable MP, guard flash caching paths, DTS address handling) and refreshes DDR configuration constants/docs/CI coverage.
Reviewed changes
Copilot reviewed 6 out of 6 changed files in this pull request and generated 3 comments.
Show a summary per file
| File | Description |
|---|---|
src/boot_ppc_start.S |
e6500-safe address loading, CCSRBAR relocation/TLB ordering fixes, VPX3‑152 TLB sizing & flash mapping adjustments, early UART debug helpers |
src/boot_ppc_mp.S |
Comment/clarity cleanup in MP boot assembly |
hal/nxp_t2080.c |
VPX3‑152 MP disable guard, flash caching guards, flash bounds checks, DTS NULL for VPX3‑152, minor synchronization improvements |
hal/nxp_t2080.h |
Updates DDR parameterization and expands MODE3–8 defines; populates additional RDB register values |
docs/Targets.md |
Expanded T2080 target documentation: board matrix, VPX3‑152 specifics, programming/recovery notes |
.github/workflows/test-configs.yml |
Adds board-specific build jobs for T2080 variants in CI |
Comments suppressed due to low confidence (1)
hal/nxp_t2080.c:400
hal_flash_enable_caching()is a no-op forBOARD_CW_VPX3152, but theDEBUG_UARTlog still prints "Flash: caching enabled" unconditionally. This makes UART logs misleading when debugging VPX3-152 boot/flash performance. Gate the log behind the same#ifndef BOARD_CW_VPX3152, or print an alternate message indicating caching is skipped/uncached on this board.
#ifndef BOARD_CW_VPX3152
/* Rewrite flash TLB entry with cacheable attributes.
* MAS2_M = memory coherent, enables caching */
set_tlb(1, 2,
FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
FLASH_TLB_PAGESZ, 1);
/* Invalidate L1 I-cache so new TLB attributes take effect */
invalidate_icache();
#endif
#ifdef DEBUG_UART
wolfBoot_printf("Flash: caching enabled (L1+L2+CPC)\n");
#endif
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Pull request overview
Copilot reviewed 15 out of 15 changed files in this pull request and generated 7 comments.
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Add VxWorks 7 64-bit boot support for the NXP T2080 / CW VPX3-152 board.
Tested on real hardware: wolfBoot signs/verifies the uVxWorks uImage,
hands off to the kernel via the ePAPR ABI with the post-
ossel=ostype264-bit memory map.
Features
software portals (mirrors CW U-Boot
set_liodns()+setup_portals()).Gated by
ENABLE_DPAA(default-on;WOLFBOOT_NO_DPAAto disable).ih_load/ih_epso the kernel is loaded to the address baked into the image.OS_64BIT=1): peripheral LAW / TLB transitionmatching CW U-Boot ostype2, isr_empty handler relocated to DDR, IVPR
retargeted, ePAPR jump (r3=DTB, r6=EPAPR magic, r7=BOOTMAPSZ).
ft_fixup_cpu:/memreserve/for spin-table /bootmap / top-of-4GB pages, plus per-CPU
status/enable-method=spin-table/cpu-release-addr.0xEF000000to free the flash VA window.Fixes
set_tlb(EA=0xC0000000, PAGESZ_2G)silently rounded the EPN to
0x80000000and shadowed DDR upper 2 GB.Fixed to 1 GB-aligned at
0xC0000000.0x100000-0x6C8BF0); moved default to0x03fe6000(matches U-Boot).cw_152_64.dtband CW U-Bootkeep DDR contiguous at low PA
0..4GB. Comments / helpers corrected.VxWorks's NTLB invalidation pass anyway.
do_boot(was onlyL1_CACHE_SZ).hal/nxp_t2080.ld: moved.gnu.version*out of/DISCARD/(binutils2.42 rejected the discard pattern).
Improvements
WOLFBOOT_PPC_PRE_OS_DUMPopt-in: full pre-jump dump (SPRs / CCSR /LAW / TLB1 / IFC / DDR / DUART / spin-table / kernel-entry bytes /
post-fixup FDT as
Fxxxxx:hex lines) for byte-level diff againstU-Boot's pre-bootm state.
nxp-t2080.config.docs/Targets.mdcovering CCSR relocation, partitionlayout, OS_64BIT trampoline, and the 64-bit memory map.